Volume: 2 Issue: 2
Year: 2025, Page: 64-69, Doi: https://doi.org/10.70968/ijeaca.v2i2.ML111
Received: July 23, 2025 Accepted: Nov. 13, 2025 Published: Dec. 12, 2025
The rapid advancement of Very Large Scale Integration (VLSI) technology has led to highly complex and densely packed circuits, increasing the probability of faults during manufacturing and operation. Traditional fault detection techniques such as Automatic Test Pattern Generation (ATPG) and fault simulation face significant challenges, including high computational cost, increased test time, and limited scalability for modern nanometer-scale circuits. To address these limitations, this research explores the application of machine learning (ML) techniques for efficient fault detection and localization in VLSI circuits. Various ML algorithms, including Support Vector Machines (SVM), Random Forests, Artificial Neural Networks (ANN), and Graph Neural Networks (GNN), are analyzed for their ability to classify and detect faults based on circuit response data. The proposed framework involves data collection through test patterns, feature extraction, model training, and fault classification. Performance is evaluated using metrics such as accuracy, precision, recall, and F1-score. The study highlights the advantages of ML-based approaches in improving fault detection accuracy, reducing testing time, and enabling scalable solutions. Additionally, it identifies existing research gaps and suggests future directions toward adaptive, real-time, and intelligent testing systems for next-generation VLSI technologies.
Keywords: Machine Learning-Based Fault Detection in VLSI Circuits
1. Bushnell ML, Agrawal VD. Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. Frontiers in Electronic Testing. 2002; Available from: https://doi.org/10.1007/b117406
2. Jha NK, Gupta S. Testing of Digital Systems. 2003; Available from: https://doi.org/10.1017/cbo9780511816321
3. Goel P. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits. IEEE Transactions on Computers. 1981; C-30 (3). Available from: https://doi.org/10.1109/tc.1981.1675757
4. Wang LT, Wu CW, Wen X. <I>VLSI Test Principles and Architectures</I>. Morgan Kaufmann. 2006; Available from: https://doi.org/10.1016/b978-012370597-6/50001-9
5. Huang Y, Abraham J. Algorithm-Based Fault Tolerance for Matrix Operations. IEEE Transactions on Computers. 1984; C-33 (6). Available from: https://doi.org/10.1109/TC.1984.1676475
6. Breiman L. Random Forests. Machine Learning. 2001; 45 (1). Available from: https://doi.org/10.1023/a:1010933404324
7. Schapire RE. The Boosting Approach to Machine Learning. An Overview. Nonlinear Estimation and Classification. 2003; Available from: https://doi.org/10.1007/978-0-387-21579-2_9
8. Mitra S, Kim KS. Machine learning applications in VLSI testing. <I>IEEE Design & Test</I>, vol. 34, no. 5, pp. 64–75, 2017.
9. Hinton GE, Salakhutdinov RR. Reducing the Dimensionality of Data with Neural Networks. Science. 2006; 313 (5786). Available from: https://doi.org/10.1126/science.1127647
10. LeCun Y, Bengio Y, Hinton G. Deep learning. Nature. 2015; 521 (7553). Available from: https://doi.org/10.1038/nature14539
11. Gaber L, Alzahrani AA, Gaddah MAA, Hammad A. Fault Detection based on Deep Learning for Digital VLSI Circuits. Procedia Computer Science. 2021; 194 Available from: https://doi.org/10.1016/j.procs.2021.10.065
12. Moness M, Habib SMF, Hossain MA. Automated Design Error Debugging of Digital VLSI Circuits. Journal of Electronic Testing. 2022; 38 (4). Available from: https://doi.org/10.1007/s10836-022-06020-z
13. Wu Z, Pan S, Chen F, Long G, Zhang C, Yu PS. A Comprehensive Survey on Graph Neural Networks. IEEE Transactions on Neural Networks and Learning Systems. 2021; 32 (1). Available from: https://doi.org/10.1109/tnnls.2020.2978386
14. Hung SC, Hsu YC, Wen HM, Rutenbar RA. Graph Neural Network-based Delay-Fault Localization for Monolithic 3D ICs. 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2022; Available from: https://doi.org/10.23919/date54114.2022.9774511
15. Shao S, Yu HY, Raghunathan A. Transferable Graph Neural Network-Based Delay-Fault Localization for Monolithic 3-D ICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2023; 42 (11). Available from: https://doi.org/10.1109/tcad.2023.3275532
16. Wen X, Li P, Ying W. Machine learning-aided test pattern generation and optimization. <I>Proc. IEEE Design, Automation and Test in Europe (DATE)</I>, 2019.
17. Silver D, Huang A, Maddison CJ, Guez A, Sifre L, van den Driessche G, <I>et al</I>. Mastering the game of Go with deep neural networks and tree search. Nature. 2016; 529 Available from: https://doi.org/10.1038/nature16961
18. Sutton RS, Barto AG. <I>Reinforcement Learning: An Introduction</I>, 2nd ed. MIT Press, 2018.
19. Tehranipoor M, Wang C. <I>Introduction to Hardware Security and Trust</I>. Springer. 2011; Available from: https://doi.org/10.1007/978-1-4419-8080-9
20. Mitra S, Seifert N, Zhang M, Shi Q, Kim KS. Robust system design with built-in soft-error resilience. Computer. 2005; 38 (2). Available from: https://doi.org/10.1109/mc.2005.70
21. Javaid A, Tahir HR, Aslam M. Machine Learning Algorithms and Fault Detection for Improved Belief Function Based Decision Fusion in Wireless Sensor Networks. Sensors. 2019; 19 (6). Available from: https://doi.org/10.3390/s19061334
22. Shaaban M, Eltawil AM, Fahmy HA. Deep learning for fault detection in integrated circuits: Advances and challenges. <I>IEEE Design & Test</I>, vol. 37, no. 5, pp. 33–41, 2020.
23. Mitra S, Kim KS. Diagnosis of intermittent and transient faults using data-driven techniques. <I>IEEE Design & Test</I>, vol. 35, no. 5, pp. 20–29, 2018.
24. El Sayed Z, Wang Z, Selmani H, Knechtel J, Sinanoglu O, Alrahis L. Graph Neural Networks for Integrated Circuit Design, Reliability, and Security: Survey and Tool. ACM Computing Surveys. 2026; 58 (4). Available from: https://doi.org/10.1145/3769081
25. Ali H, Khan T, Khan Z. Fault detection using machine learning-based dynamic independent component analysis. <I>Microelectronics Reliability</I>, vol. 150, 2024.
26. Moness M, Habib SMF. Semi-supervised deep learning models for VLSI fault detection. <I>IEEE Transactions on Very Large Scale Integration (VLSI) Systems</I>, vol. 30, no. 6, pp. 897–908, 2022.
27. Saha S, Siddiqui M. Machine learning-based fault detection framework for VLSI circuits using ATPG datasets. <I>Proc. International Conference on Emerging Technologies</I>, 2024.
28. Wen X, Li P, Ying W. Machine learning-aided test pattern generation and optimization. <I>Proc. IEEE DATE</I>, 2019.
29. Javaid A, Tahir HR, Aslam M. Machine Learning Algorithms and Fault Detection for Improved Belief Function Based Decision Fusion in Wireless Sensor Networks. Sensors. 2019; 19 (6). Available from: https://doi.org/10.3390/s19061334
30. DfX-NYUAD. <I>GNN4IC: Graph neural networks for integrated circuits—A survey and benchmark collection</I>. GitHub Repository, 2024.
31. Data-driven fault localization in VLSI chips using semi-supervised learning. <I>International Journal of VLSI Design & Communication Systems</I>, vol. 16, no. 2, 2025.
© 2025 Somwanshi & Vyavhare. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
Somwanshi S, Vyavhare V. Machine Learning-Based Fault Detection in VLSI Circuits. 2025;2(2):64-69.
https://doi.org/10.70968/ijeaca.v2i2.ML111